Hierarchical Model Partitioning for Parallel VLSI-Simulation Using Evolutionary Algorithms

Haupt, Reiner
Hering, Klaus
Petri, Udo
Villmann, Thomas
Parallelization of VLSI-simulation exploiting model-inherent parallelism is a promising way to accelerate veriflcation processes for whole processor designs. Thereby partitioning of hardware models in?uences the e?ciency of following parallel simulations essentially. Based on a formal model of Parallel Cycle Simulation we introduce partition valuation combining communication and load balancing aspects. We choose a 2-level hierarchical partitioning scheme providing a framework for a mixture of experts strategy. Considering a complete model of a PowerPC 604 processor, we demonstrate that Evolutionary Algorithms can be applied successfully to our model partitioning problem on the second hierarchy level, supposing a reduced problem complexity after fast pre-partitioning on the flrst level. For the flrst time, we apply superpositions during execution of Evolutionary Algorithms, resulting in a faster decreasing fltness function and an acceleration of population handling.
Appeared / Erschienen in: 
Proceedings of the 5th European Congress on Intelligent Techniques and Soft Computing (EUFIT'97), S. 804-808, Verlag Mainz, 1997.
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1997-32.pdf340.39 KB